Location: Kolkata
Company: HPE
What You’ll Do
- You will be exposed to the latest verification methodologies like UVM and enable complex feature verification suites.
- Architect and Develop block level verification environments for sub-system and full chip using System Verilog and UVM methodology. (30%)
- Define, architect, code, and deliver verification suites/tests for ASICs that enable faster, denser, feature-rich systems. Use various front-end simulator tools (VCS/NC) to perform this activity. (25%)
- Verify large ASIC blocks independently and rapidly and sign off them for tape-out with analysis of code coverage, functional coverage and gate-level simulation. (30%)
- Work closely with logic designers to resolve bugs and software developers to assist in software and bring-up development. (10%)
- Develop Perl, Python and/or shell scripts to improve current verification infrastructure/methodology (5%)
What You Need to Bring
- Strong skills in UVM, SystemVerilog, or similar
- 5 plus years of DV experience
- A problem-solving mindset and attention to detail
- ASIC Verification using System Verilog
- A team player’s approach and the drive to innovate
- Experience in constrained-random verification is a strong plus
- Experience with verification methodology like OVM/VMM/UVM
- Perl/Tcl scripting is strongly preferred
- Experience verifying networking protocols such as Ethernet, is desirable
- Strong problem-solving and ASIC debugging skills
- MSEE or BSEE is required with 5 plus of experience
Additional Skills
Accountability, Accountability, Action Planning, Active Learning, Active Listening, Agile Methodology, Agile Scrum Development, Analytical Thinking, Bias, Coaching, Creativity, Critical Thinking, Cross-Functional Teamwork, Data Analysis Management, Data Collection Management (Inactive), Data Controls, Design, Design Thinking, Empathy, Follow-Through, Group Problem Solving, Growth Mindset, Intellectual Curiosity (Inactive), Long Term Planning, Managing Ambiguity {+ 5 more}