Location: Bengaluru
Company: AMD
The AMD Cores design & verification group develops high-end, next generation CPU’s that power different AMD SoC’s which are eventually set to change the course of how computing is visualized. The engineering teams are distributed across US and India. The CPU verification team in India is one of AMD India’s first teams & involved in contributing to the tape out of numerous AMD systems. As part of the CPU Design Verification team, our team will be responsible for the maintainability & scalability of RTL & testbench environment that is used for development & verification of the design. As always, the team is dedicated to come up with innovative solution to overcome new challenges related to specific project requirements and time-to-market.
Key Responsibilities
- Will work with different stake holders in getting a thorough understanding of high-level feature/s & get clarification(if any). Also, evaluate cross-feature dependencies.
- After feature understanding, populate high level testplan that details out how we plan(Stimulus, debug, coverage) to verify the feature & what we cover/don’t cover as a part of the feature verification. Get it reviewed & incorporate feedback.
- Develop directed/random test cases to target the feature bring-up. Debug fails(debug needs an understanding of computer architecture, micro-architecture & TB environment), file RTL/Verif bugs, fix testbench issues.
- Ensure feature health is stable & in parallel work on evaluating stimulus coverage. If needed, tweak/add stimulus as appropriate.
- If the feature demands, develop new C++ checkers. All this while learning & understanding uarch is an integral part.
- Work on ensuring 100% FCOV that might involve developing new stimulus. Also, it might demand working with other feature owners to close on cross-feature coverage.
- On a need basis, work on Post-Si bug recreation.
Skills and Experience Requirements
- B.E/B.Tech/M.E/M.Tech in Computer Science/Electrical/Electronic Engineering.
- 5+ years of experience in CPU verification.
- Good understanding about basics of computer architecture & digital systems
- Understanding of assembly(x86) code.
- Good understanding of Verilog, System Verilog, C++. Knowledge of shell/perl scripting is a plus.
- Understanding of Formal Verification methodology (with tools VSI-FV/JASPER/IFV/IEV) is a plus.
- Should be a good team player, quick thinker, pro-active, adaptable & outspoken/approachable.
- Must communicate well both written and orally.
- Must be well-organised and should be able to multitask well with due diligence on closing his/her tasks.