By leveraging high-speed switching, integrated body-diodes, and advanced thermal design with AlN substrates, the module delivers over 100% more output current while maintaining stability under extreme conditions—perfect for 1,500 VDC inverter systems in solar and wind power.
Mitsubishi Electric’s latest SiC-MOSFET module—SiC-LV100—is a bold leap in power electronics designed for renewable energy systems operating at 1,500 VDC. The all-SiC solution features a fully optimized structure that balances high current density, efficient thermal dissipation, and robust switching performance—crucial for large-scale solar and wind power inverters.
The key features are:
- Optimized for 1,000 VAC / 1,500 VDC 2-level inverter topologies
- Delivers over 100% higher output current than conventional Si-IGBT modules
- Features ultra-low on-resistance of 1.9 mΩ at 150°C (under development)
- Enables low conduction losses and high-speed switchingPowered by second-generation planar SiC-MOSFET technology
At its core, it employs only SiC-MOSFETs, eliminating the need for separate freewheeling diodes. The built-in body diode within the MOSFETs supports bidirectional operation, enhancing conduction efficiency during dead-time and reducing module footprint. Mitsubishi’s design enables a current rating of up to 1,800 A (under development) with compact form factor—pushing the limits of power density.
One of the standout features is the use of a ceramic insulation structure with an AlN (aluminum nitride) substrate, offering superior thermal conductivity compared to conventional SLC structures. Thermal resistance from chip to heatsink is reduced by 11%, keeping junction temperatures lower and ensuring reliable performance even under high switching frequencies.
However, integrating a large number of parallel-connected MOSFET chips introduces design complexity. Variations in gate and source impedance can cause uneven current distribution and gate voltage oscillations, potentially leading to performance instability. Mitsubishi counters this with a precision-optimized internal layout that balances source inductance across chips and suppresses resonant interference. The result? A 70% reduction in inductance variation and enhanced current sharing.