Location: Bengaluru
Company: Sykatiya Technologies
This is a full-time Work from Office position, allowing for a balance between in-office presence and remote work. Responsibilities include RTL synthesis for complex designs, timing constraint development, timing closure activities, performing power optimizations, collaborating with cross-functional teams, and ensuring design signoff.
Sykatiya Technologies Pvt Ltd (India/US) is looking for engineers who don’t just run synthesis… but actually fix PPA(Power, Performance, Area).
If you’ve worked on RTL Synthesis end-to-end, handled real timing closure challenges, and understand the “why” behind constraints — this role is for you.
What we’re looking for:
- Experience: 3 to 10 years
- Strong experience in RTL / Logic Synthesis
- Hands-on with Synopsys Design Compiler or Cadence Genus
- Solid STA expertise using Synopsys PrimeTime
- Exposure to LEC / Spyglass / linting is a plus
- Engineers who can think beyond tools and own PPA (Power, Performance, Area)
Openings: 10
Notice Period: Immediate to 30 days
You’ll work closely with RTL, PD, and DFT teams — not just executing tasks, but influencing real silicon outcomes.
Apply: [email protected]